1. Field of Invention
This invention relates to the handling of FIFO communication queues in a low processing power 8-bit microcontroller.
2. Discussion of Prior Art
The programming of a given process or algorithm in a low processing power 8-bit microcontroller (8-BMC), consisting of receiving an input data and executing a process over such data to obtain a result, can contain the elements shown on FIG. 1.
An 8-BMC 110 is progranmied with a bi-directional process 112. Such process uses a banked RAM 114, which consists of a series of memory banks B1, B2, B3 . . . Bn controlled by the process. The RAM (random access memory) 114 comprises the internal 8-bit registers available in the microcontroller, any external RAM, or any combination of both. In any case, each bank is considered a memory buffer. Two interfaces (116a, 116b) connect the 8-BMC 110 to external systems or microprocessors not shown on the figure. The process 112 takes a size-defined packet of bytes coming from the interface 116a and stores it in any of the memory banks available in the RAM 114 to finally apply the process itself and return a result through the interface 116b. In the same manner, any information coming from, the interface 116b goes through a similar mechanism with an inverse process to obtain an output at interace 116a. 
Those skilled in the art can assume such interfaces as any kind of communication standards widely used in microcomputers, like an asynchronous serial port or a synchronous SPI (Serial Peripheral Interface) port, an I2C master-slave port, a parallel slave port or any other user-defined method of communication. It is very common to find the above communication standards implemented on the hardware itself on an 8-BMC. A hardware implementation avoids the need of programming the standard, increasing the device""s general performance. Rather, the sending and receiving mechanism is made through some specialized memory positions accessible by the program.
Due to the possible use of different interfaces, the time needed to transfer an information packet through the interface 116a won""t be the same as a transfer at interface 116b. For example, a serial transfer will last longer than a parallel information transfer. Furthermore, the size of the information could be different from interface 116a to interface 116b, since there is a process 112 involved. Such process could be for example a communication protocol encoder-decoder or a security verification algorithm, so the information coming in from one interface could be larger or smaller than the information coming out to the second interface.
Furthermore, the systems behind each interface could have different processing power and speed, and usually the faster one could handle more information by time unit than the slower one. Additionally, the amount of information sent or received by those systems can vary dynamically according to its own program or process.
Thus the interface speed, the size of the information packets, the involved kind of process and the behavior of the external systems determine the amount of information passing through the 8-BMC. In order to handle the information going from interface 116a to interface 116b or vice versa, two different memory queues are needed to temporally store and process each packet.
A static assignment of memory buffers to each queue is a simple solution. However, any variation on the mentioned factors could increase or decrease in a given moment the traffic of packets traveling in any direction. Since the buffers assignment is static, those assigned to the low traffic transfer would be unused, while the high traffic transfer could not be assisted because of the lack of memory space.
In the recent past there have been different approaches to the queue management mechanism (e.g. U.S. Pat. No. 6,137,807). That invention proposes a temporal buffering of data in the form of logical queues to supply a series of output ports. However, such invention is oriented to data buffering and queue control only, without the possibility of including any kind of data processing or data transformation. That invention also proposes the use of a specialized ASIC (application specific integrated circuit) to physically implement the memory controller. Even when an ASIC optimizes the performance, it does not offer the programmable flexibility of a microcontroller. Furthermore, that implementation considers unidirectional data flow by defining an input-only source and an output-only destination.
It is the intention of this invention to overcome such limitations providing an efficient method to handle multiple communication queues capable of transporting information packets between two or more communication interfaces with a bidirectional communication.
The present invention comprises a method for handling multiple logical communication queues sharing one physical memory space. Having a banked RAM, each bank is used as an individual memory buffer independent of the existing type of queues. Since there is no static memory buffer assignment to each type of queue, all banks are available for all queues, making efficient use of memory resources even when the traffic generated by each queue can vary dynamically.
The hardware platform is an 8-bit microcontroller which contains both a programmed process to be applied to any incoming packet and the queue management mechanism needed to temporarily store each packet.
A simple mechanism to handle the available memory and queues has been created in accordance to the processing power of the microcontroller, by reducing the complexity of the involved algorithm and the amount of memory needed to control the queues.
Accordingly, several objects and advantages of the present invention are: a) To provide a memory management method capable of handling multiple queues needed to accomplish a process of receiving input information to generate an output result.
b) To provide the concurrent handling of logical queues sharing the same physical banked memory.
c) To provide an efficient mechanism to handle each logical memory queue, suitable to a low processing power 8-bit microcontroller.
Other objects and advantages of this invention will become apparent from a consideration of the ensuing description and drawings.